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Other articles related with "TN4":
1332 Yu Qing-Dong, Zhou Li, Chen Jie
  Hardware-efficient Motion Compensation Architecture for Multi-standard Video Decoder
    JEIT   2011 Vol.33 (6): 1332-1338 [Abstract] (2307) [HTML 1 KB] [PDF 473 KB] (846)
1481 Qiu Xiao-Qiang, Yang Hai-Gang, Zhou Fa-Biao, Xie Yuan-Lu
  Analysis of Delay-power Model of Long Chain and Optimization Based on Hybrid Evolution Particle Swarm Algorithm
    JEIT   2011 Vol.33 (6): 1481-1486 [Abstract] (1979) [HTML 1 KB] [PDF 425 KB] (1079)
938 Peng Yao, Zhou Duan, Yang Yin-Tang, Zhu Zhang-Ming
  A Novel High-speed Delay-independent Asynchronous to Synchronous Communication Interface
    JEIT   2011 Vol.33 (4): 938-944 [Abstract] (2326) [HTML 1 KB] [PDF 399 KB] (1089)
945 Liu Yi, Zhong Guang-De, Yang Yin-Tang
  A Low Power Adaptive Spatio-temporal Bus Coding for Crosstalk Avoidance
    JEIT   2011 Vol.33 (4): 945-950 [Abstract] (2017) [HTML 1 KB] [PDF 363 KB] (896)
717 Chen Yun-Bi, Guo Li, Li Zheng-Dong, Chi Ling-Hong
  An Efficient Parallel Architecture for One-bit Transform Based Motion Estimation
    JEIT   2011 Vol.33 (3): 717-722 [Abstract] (2369) [HTML 1 KB] [PDF 360 KB] (841)
723 Yang Jin-Lin, Yang Hai-Gang
  Conflict-free Access Mechanism and “Bit Identifying” Technique Research of Reconfigurable Memories
    JEIT   2011 Vol.33 (3): 723-728 [Abstract] (2930) [HTML 1 KB] [PDF 501 KB] (857)
749 Liu Su-Juan, Zhang Te, Chen Jian-Xin
  Design and Implementation of a Hardware-efficient Novel Digital Interpolation Filter Applied to Stereo Audio Sigma-Delta DAC
    JEIT   2011 Vol.33 (3): 749-753 [Abstract] (2791) [HTML 1 KB] [PDF 387 KB] (1121)
448 Wang Yi-Mu, Pan Bin, Yan Xiao-Lang
  An Improved Color-based Particle Filter and Its Full Hardware Implementation
    JEIT   2011 Vol.33 (2): 448-454 [Abstract] (2943) [HTML 1 KB] [PDF 615 KB] (2022)
2901 Li Yuan-Jin, Zhang Wan-Cheng, Wu Nan-Jian
  A Fast Traffic Lane Detection System Based on Parallel Processors and FPGA Implementation
    JEIT   2010 Vol.32 (12): 2901-2906 [Abstract] (2829) [HTML 1 KB] [PDF 500 KB] (1163)
2993 Yang Yin-Tang, Tong Xing-Yuan, Zhu Zhang-Ming, Guan Xu-Guang
  A 10-bit 200 kS/s 65 nm CMOS SAR ADC IP Core
    JEIT   2010 Vol.32 (12): 2993-2998 [Abstract] (3129) [HTML 1 KB] [PDF 413 KB] (2071)
2740 Zhong Lun-Gui, Yang Hai-Gang, Liu Fei, Gao Tong-Qiang, Zhang Hui
  A Fully Integrated CMOS Complex Filter for IEEE802.15.4 Standard
    JEIT   2010 Vol.32 (11): 2740-2745 [Abstract] (2541) [HTML 1 KB] [PDF 318 KB] (1199)
2772 Chen Fei-Hua, Duo Xin-Zhong, Sun Xiao-Wei
  A CMOS Wideband Variable Gain LNA with Novel Gain Control Method
    JEIT   2010 Vol.32 (11): 2772-2775 [Abstract] (2946) [HTML 1 KB] [PDF 232 KB] (1044)
2095 Chen Guang-Hua, Zhu Jing-Ming, Liu Ming, Zeng Wei-Min
  Dual-field Modular Multiplication Algorithm and Modular Inversion Algorithm with VLSI Implementation
    JEIT   2010 Vol.32 (9): 2095-2100 [Abstract] (2977) [HTML 1 KB] [PDF 347 KB] (1396)
2023 Li Wei, Yang Hai-Gang, Huang Juan
  Optimal Design for FPGA Interconnect Based on Combinations of Single-driver and Multi-driver Wires
    JEIT   2010 Vol.32 (8): 2023-2027 [Abstract] (2547) [HTML 1 KB] [PDF 260 KB] (829)
1389 Qu Xiao-gang①②; Yang Hai-gang①
  Design Technique for Generating Large Delay in Area-Constraint Power-On Reset Circuit
    JEIT   2010 Vol.32 (6): 1389-1394 [Abstract] (2682) [HTML 1 KB] [PDF 466 KB] (1649)
1395 Cui Xiu-hai①; Yang Hai-gang①; Gong Xiao①②; Huang Juan①②; Tan Yi-tao①②
  A Research on Subsection Progressive Optimization Placement Algorithm of FPGA
    JEIT   2010 Vol.32 (6): 1395-1400 [Abstract] (2493) [HTML 1 KB] [PDF 346 KB] (745)
1515 Zhao Jing-jing①; Li Li①; Pan Hong-bing①; Xu Jun②; Wu Zhi-gang①; Lin Jun①
  High-Speed Hardware Implementation for GCM in IEEE802.1AE
    JEIT   2010 Vol.32 (6): 1515-1519 [Abstract] (2324) [HTML 1 KB] [PDF 260 KB] (1274)
1012 Hao Zhi-gang①②; Yang Hai-gang①; Zhang Chong①②; Wu Qi-song①②; Yin Tao①
  An Improved Digital Decimation Filter for Sigma-Delta ADC
    JEIT   2010 Vol.32 (4): 1012-1016 [Abstract] (3133) [HTML 1 KB] [PDF 244 KB] (2499)
705 Dong Gang①②; Yang Hai-gang①
  Reducing Undetected Error Rate of CRC Coding Based on Lossless Compression and Implement in Circuits
    JEIT   2010 Vol.32 (3): 705-709 [Abstract] (2908) [HTML 1 KB] [PDF 229 KB] (1266)
714 Yang Hai-gang①; Sun Jia-bin①②; Wang Wei③
  An Overview to FPGA Device Design Technologies
    JEIT   2010 Vol.32 (3): 714-727 [Abstract] (3728) [HTML 1 KB] [PDF 538 KB] (3248)
464 Yin Shu-juan,Li Xiang-yu,Sun Yi-he
  Design of 16 bit Low-Voltage Low-Power ΣΔ Modulator with Standard Digital Technology
    JEIT   2010 Vol.32 (2): 464-469 [Abstract] (2429) [HTML 1 KB] [PDF 592 KB] (966)
203 Yin Tao①,Yang Hai-gang①,Zhang Chong①②,Wu Qi-song①②,Jiao Ji-wei③,Mi Bin-wei③
  A Low-Noise Readout Circuit for Bulk Micro-Machined Capacitive Gyroscope
    JEIT   2010 Vol.32 (1): 203-209 [Abstract] (2270) [HTML 1 KB] [PDF 579 KB] (959)
210 Zhou Wen,Liu Hong-xia,Kuang Qian-wei,Gao Bo,Cao Lei
  Quantitative Studies Redundant Object Defect in IC for Signal Crosstalk
    JEIT   2010 Vol.32 (1): 210-213 [Abstract] (2840) [HTML 1 KB] [PDF 270 KB] (923)
214 Wang Peng-jun,Zeng Xiao-pang
  Design of New Adiabatic Digital Comparator with Pre-Computational Function
    JEIT   2010 Vol.32 (1): 214-218 [Abstract] (2676) [HTML 1 KB] [PDF 306 KB] (886)
2980 Xue Ji-ying①; Sun Nan②; Zhang Wei③; Zhang Wen-jun①; Yu Zhi-ping①
  A Novel Algorithm for Circuit Partitioning at Transistor Level
    JEIT   2009 Vol.31 (12): 2980-2983 [Abstract] (2242) [HTML 1 KB] [PDF 247 KB] (958)
2762 Cai Gang①②; Yang Hai-gang①
  A “Selective Registering” Technique for Design of an Embedded Programmable Memory
    JEIT   2009 Vol.31 (11): 2762-2766 [Abstract] (2333) [HTML 1 KB] [PDF 586 KB] (925)
2767 Li Jian-wei; Dong Gang; Yang Yin-tang; Wang Zeng
  Statistical RLC Interconnect Delay Considering Process Variations
    JEIT   2009 Vol.31 (11): 2767-2771 [Abstract] (2461) [HTML 1 KB] [PDF 277 KB] (979)
1980 Hu Zhi-hua①②; Xu Jie②
  State Space Models of RLGC Interconnect with Super High Order in Time Domain and Its Research
    JEIT   2009 Vol.31 (8): 1980-1984 [Abstract] (2656) [HTML 1 KB] [PDF 276 KB] (1648)
1775 Ma Wei-wei; Wang You-ren; Shi Yu; Cui Jiang
  Reconfigurable Analog Circuit and Application Design Based on Operational Transconductance Amplifier
    JEIT   2009 Vol.31 (7): 1775-1778 [Abstract] (2778) [HTML 1 KB] [PDF 222 KB] (1168)
1479 Liu Jun-hua①②; Yang Hai-gang①; Li Wei①②
  A Novel Testing Method Based on Matching Theory for Three Stage Interconnect Network in FPGA
    JEIT   2009 Vol.31 (6): 1479-1482 [Abstract] (2599) [HTML 1 KB] [PDF 307 KB] (912)
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