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An Improved Digital Decimation Filter for Sigma-Delta ADC |
Hao Zhi-gang①②; Yang Hai-gang①; Zhang Chong①②; Wu Qi-song①②; Yin Tao① |
①Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China; ②Graduate University of Chinese Academy of Sciences, Beijing 100049, China |
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Abstract Usually in a sigma-delta ADC, the digital filter takes most of the chip area. In this paper, a novel digital filer topology is proposed, in which the differentiator is constructed with a control unit and an adder instead of the multiple of adders in the Hogenauer structure filter, so that the digital circuit area should be reduced. A fourth order digital filter employing such topology is implemented in a Cyclone-II FPGA, and costs chip resources 29 percent less than in a Hogenauer structure.
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Received: 02 March 2009
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Corresponding Authors:
Hao Zhi-gang
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