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| A Research on Subsection Progressive Optimization Placement Algorithm of FPGA |
| Cui Xiu-hai①; Yang Hai-gang①; Gong Xiao①②; Huang Juan①②; Tan Yi-tao①② |
| ①Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China; ②Graduate University, Chinese Academy of Sciences, Beijing 100039, China |
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Abstract A novel FPGA simulated annealing placement algorithm is proposed to improve the routability and optimize the length of wires. Different cost functions are applied to different temperature range. In high temperature stage, the half perimeter method is utilized to fast optimize the placement; while in low temperature stage, a variable factor is added into the cost function and the reasonable temper process is also used to improve the quality of placement. Experiment results demonstrate that, compared with the VPR, the proposed method requires 6% fewer routing tracks and the length of wire is 4~23% shorter.
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Received: 12 December 2008
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Corresponding Authors:
Yang Hai-gang
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LIANG Huaguo, SUN Hongyun, SUN Jun, HUANG Zhengfeng, XU Xiumin, YI Maoxiang, OUYANG Yiming, LU Yingchun, YAN Aibin. FPGA-based Soft Error Sensitivity Analysis Method for Microprocessor[J]. JEIT, 2017, 39(1): 245-249. |
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2010, Vol. 32 
