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| A 10-bit 200 kS/s 65 nm CMOS SAR ADC IP Core |
| Yang Yin-tang①② Tong Xing-yuan① Zhu Zhang-ming① Guan Xu-guang① |
| ①Microelectronics Institute of Xidian University, Xi’an 710071, China ②Key Lab of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices in Xidian University, Xi’an 710071, China |
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Abstract Based on 65 nm CMOS low leakage process, an 8-channel 10-bit 200 kS/s SAR (Successive Approximation Register) ADC (Analog-to-Digital Converter) IP core for touch screen SoC is realized. In the D/A converter design, a “7MSB (Most-Significant-Bit)-plus-3LSB (Least-Significant-Bit)” R-C hybrid conversion approach is utilized to reduce the area of the converter, and by reusing the MSB resistor string, the matching requirement of the capacitors is alleviated. With a low-offset pseuso-differential comparison approach, the input offset of the comparator is reduced. In the layout design, capacitor array symmetrical layout routing approach and resistor string dummy surrounding method are utilized to improve the matching performance. The area of the IP core is 322 μm×267 μm. This converter operates with a 2.5 V analog supply and a 1.2 V digital supply. With the input frequency of 1.03 kHz at 200 kS/s sampling rate, the SFDR (Spurious-Free Dynamic Range) and ENOB (Effective Number Of Bits) are measured to be 68.2 dB and 9.27 respectively, and the power dissipation is just measured to be 440 μW. The design results prove the applicability of this converter to embedded SoC.
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Received: 02 July 2010
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Corresponding Authors:
Tong Xing-yuan
E-mail: mayxt@126.com
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2010, Vol. 32 
