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| Hardware-efficient Motion Compensation Architecture for Multi-standard Video Decoder |
| Yu Qing-dong Zhou Li Chen Jie |
| Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China |
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Abstract To solve the problem of Motion Compensation (MC) for multiple standards efficiently, a modified hardware-efficient computing architecture of MC interpolation for multiple standards is developed with the proposed Rounding Last (RL) and Diagonal Two Step (DTS) strategies. A re-configurable MC interpolation hardware based on the new computing architecture is implemented efficiently based on the variable block size. Compared with the fixed-size 4×4 block-based MC in JM8.4, the bandwidth reduction is about 27%~50%, and the average burst length of each access to the external memory is improved to 1.22~2.25 times longer. When work at 125 MHz, the MC hardware is capable to accomplish the real-time decoding of video streams of the supported standards at 1080 p (1920×1080) 30 f/s.
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Received: 20 October 2010
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Corresponding Authors:
Yu Qing-dong
E-mail: yuqingdong@ime.ac.cn
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2011, Vol. 33 
