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| Optimal Design for FPGA Interconnect Based on Combinations of Single-driver and Multi-driver Wires |
| Li Wei①② Yang Hai-gang① Huang Juan①② |
①(Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China)
②(Graduate University of Chinese Academy of Sciences, Beijing 100049, China) |
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Abstract Single-driver directional wires and multi-driver directional wires can both be used for FPGA interconnect. This paper compares them in area, performance, and their effect on topology of the routing architecture. Then a new type of FPGA routing architecture is proposed that utilizes a mixture of single-driver and multi-driver wires combined with various wire lengths and a two-stage optimization method is used to obtain the best routing architecture. Extensive experiments show that the best architecture optimized by area-delay product is 50% length 6 wires with single-driver, 25% length 8 wires with multi-driver and 25% length 8 wires with single-driver. This results in FPGA with 57%～86% gain in area-delay product.
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Received: 14 July 2009
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Corresponding Authors:
Yang Hai-gang
E-mail: ic_design_group@mail.ie.ac.cn
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| [1] |
LIANG Huaguo, SUN Hongyun, SUN Jun, HUANG Zhengfeng, XU Xiumin, YI Maoxiang, OUYANG Yiming, LU Yingchun, YAN Aibin. FPGA-based Soft Error Sensitivity Analysis Method for Microprocessor[J]. JEIT, 2017, 39(1): 245-249. |
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2010, Vol. 32 
