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| A Novel Algorithm for Circuit Partitioning at Transistor Level |
| Xue Ji-ying①; Sun Nan②; Zhang Wei③; Zhang Wen-jun①; Yu Zhi-ping① |
| ①Institute of Microelectronics, Tsinghua University, Beijing 100084, China; ②School of Engineering and Applied Sciences Harvard University, MA 02138, USA; ③School of Electrical and Computer Engineering, Minnesota University, MN 55101, USA |
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Abstract As the size of VLSI circuits keeps growing, the quality of circuit partitioning for parallel simulation is becoming increasingly crucial. In view of the fact that the present algorithms cannot guarantee the size balance and minimize the cut-signals among partitions simultaneously, a novel algorithm for circuit partitioning at transistor level is presented. The proposed algorithm first conducts clustering procedure to obtain a good initial partition result, and then makes an adjustment procedure to achieve well-balanced partitions with fewer cut-signals. The excellent performance of the new algorithm is demonstrated on several industrial circuits. Compared with the COPART algorithm which is widely used, the size discrepancy among different partitions and the number of cut-signals obtained using the new algorithm decrease by 25% and 18% on average, respectively.
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Received: 02 February 2009
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2009, Vol. 31 
