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| A Novel Testing Method Based on Matching Theory for Three Stage Interconnect Network in FPGA |
| Liu Jun-hua①②; Yang Hai-gang①; Li Wei①② |
①Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China;
②Graduate University of the Chinese Academy of Sciences, Beijing 100039, China |
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Abstract Aimed to testing interconnect network that includes 3-stage programmable switches in FPGA, this paper proposes a novel size-independent approach based on a matching theory to minimize the number of test configurations. By constructing the graph of structure test, this paper presents a slicing scheme based on the path pace of the graph, and a method that applies the minimum coverage and maximum matching principle from the graph theory to obtain the minimum number of test configurations. For different interconnect network structure, the number of test configurations in the proposed method is reduced by at least 10% compared with other methods.
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Received: 28 April 2008
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LIANG Huaguo, SUN Hongyun, SUN Jun, HUANG Zhengfeng, XU Xiumin, YI Maoxiang, OUYANG Yiming, LU Yingchun, YAN Aibin. FPGA-based Soft Error Sensitivity Analysis Method for Microprocessor[J]. JEIT, 2017, 39(1): 245-249. |
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2009, Vol. 31 
