电子与信息学报
   
  
   Home  |  About Journal  |  Ethics Statement  |  Editorial Board  |  Instruction  |  Subscriptions  |  Contacts Us  |  Message  |  Chinese
电子与信息学报
OFFICE ONLINE
　·Author Center
　·Peer Review
　·Editor Work
　·Office Work
　·Editor-in-chief
 
JOURNAL
　·Forthcoming Articles
　·Current Issue
　·Next Issue
　·Archive
　·Advanced Search
　·Archive By Volume
　·Archive By Subject
　·Email Alert
　·
 
Hot Paper
　·Top Cited
　·TOP Read Articles
　·TOP Download Articles
 
Other articles related with "TN402":
2487 DAI Zibin, YI Suwen, LI Wei, NAN Longmei
  Research and Design of Efficient Parallel Processing Architecture for Elliptic Curve Cryptographic Processor
    JEIT   2017 Vol.39 (10): 2487-2494 [Abstract] (168) [HTML 1 KB] [PDF 1273 KB] (452)
499 LIU Yang, YANG Yintang, LI Di, SHI Zuochen
  Body Biasing Linearization Technique for Wireless Body Area Network Transmitter
    JEIT   2017 Vol.39 (2): 499-503 [Abstract] (210) [HTML 1 KB] [PDF 948 KB] (509)
2397 HUANG Zhihong, LI Wei,YANG Liqun, JIANG Zhenghong, WEI Xing,LIN Yu, YANG Haigang
  An Input Crossbar Optimisation Method for And-inverter Cone Based FPGA
    JEIT   2016 Vol.38 (9): 2397-2404 [Abstract] (205) [HTML 1 KB] [PDF 1179 KB] (382)
2113 LI Yue, CAI Gang, LI Tianwen, YANG Haigang
  Propagation Mechanism of Single Event Transient and Soft Error Rate Analysis Method Based on Four-value Pulse Parameters Model
    JEIT   2016 Vol.38 (8): 2113-2121 [Abstract] (210) [HTML 1 KB] [PDF 476 KB] (598)
2122 HUANG Guocheng, YIN Tao, ZHU Yuanming, XU Xiaodong, ZHANG Yachao, YANG Haigang
  A -100 dB Power Supply Rejection Ratio Non-bandgap Voltage Reference
    JEIT   2016 Vol.38 (8): 2122-2128 [Abstract] (202) [HTML 1 KB] [PDF 965 KB] (779)
1831 WU Jin, JIANG Qi, ZHENG Lixia, SUN Dongchen, SONG Ke, SUN Weifeng
  Research on Low Bit Error Rate Encoding Method for Data Latch Processing
    JEIT   2016 Vol.38 (7): 1831-1837 [Abstract] (169) [HTML 1 KB] [PDF 549 KB] (550)
3030 Huang Zhi-hong, Yang Hai-gang, Yang Li-qun, Li Wei, Jiang Zheng-hong, Lin Yu
  Interconnect Architecture of a Novel And-inverter Cone Based FPGA Cluster
    JEIT   2015 Vol.37 (12): 3030-3040 [Abstract] (253) [HTML 1 KB] [PDF 2640 KB] (763)
2521 Yang Li-qun, Li Wei, Huang Zhi-hong, Sun Jia-bin, Yang Hai-gang
  Circuit Characteristics-driven Semi-supervised Modelling Approach for Accelerating FPGA Design Space Exploration
    JEIT   2015 Vol.37 (10): 2521-2528 [Abstract] (244) [HTML 1 KB] [PDF 852 KB] (697)
1937 Lan Ya-zhu,Yang Hai-gang, Lin Yu
  Design of Dynamic Adaptive LDPC Decoder Based on FPGA
    JEIT   2015 Vol.37 (8): 1937-1943 [Abstract] (359) [HTML 1 KB] [PDF 339 KB] (938)
1769 Jiang Zheng-hong, Lin Yu, Huang Zhi-hong, Yang Li-qun, Yang Hai-gang
  Mapper for AIC-based FPGAs
    JEIT   2015 Vol.37 (7): 1769-1773 [Abstract] (377) [HTML 1 KB] [PDF 673 KB] (677)
468 Yu Wei, Yang Hai-Gang, Liu Yang, Huang Juan, Cai Bo-Rui, Chen Rui
  A Statistical Static Timing Analysis Incorporating Process Variations with Spatial Correlations
    JEIT   2015 Vol.37 (2): 468-476 [Abstract] (407) [HTML 1 KB] [PDF 419 KB] (800)
206 CHEN Rui, Yang Hai-Gang, Wang Fei, Jia Rui, Yu Wei
  Design of Multi-standard Discrete Cosine Transform  Based on Coarse-grained Reconfigurable Array
    JEIT   2015 Vol.37 (1): 206-213 [Abstract] (909) [HTML 1 KB] [PDF 377 KB] (616)
2251 Chen Rui, Yang Hai-Gang, Wang Fei, Jia Rui, Wang Xin-Gang
  Coarse-grained Reconfigurable Array Based on Self-routing Interconnection Network
    JEIT   2014 Vol.36 (9): 2251-2257 [Abstract] (991) [HTML 1 KB] [PDF 475 KB] (1474)
2278 Yao Mao-Qun, Zhang Li-Bin, Geng Liang
  Design of Current-mode CMOS Pulse-triggered D Flip-Flops
    JEIT   2014 Vol.36 (9): 2278-2282 [Abstract] (1313) [HTML 1 KB] [PDF 273 KB] (1058)
2010 Shu Yi, Cai Gang, Yang Hai-Gang
  A Mixed Method of Leakage Optimization for Gate-level Netlist
    JEIT   2014 Vol.36 (8): 2010-2015 [Abstract] (1364) [HTML 1 KB] [PDF 276 KB] (778)
2016 Wu Rui-Zhen, Yang Yin-Tang, Zhang Li, Zhou Duan
  An Improved High-speed Lottery Bus Arbiter
    JEIT   2014 Vol.36 (8): 2016-2022 [Abstract] (1135) [HTML 1 KB] [PDF 256 KB] (776)
1258 Du Shi-Min, Xia Yin-Shui, Chu Zhu-Fei, Huang Cheng, Yang Run-Ping
  A Stable Fixed-outline Floorplanning Algorithm for Soft Module
    JEIT   2014 Vol.36 (5): 1258-1265 [Abstract] (1210) [HTML 1 KB] [PDF 410 KB] (1028)
758 Yu Ze-Qi, Fan Yang-Yu, Shi Long-Fei, Lv Guo-Yun
  A Pseudo Natural Sampling Algorithm for Digital Class D Power Amplifiers
    JEIT   2014 Vol.36 (3): 758-762 [Abstract] (1252) [HTML 1 KB] [PDF 306 KB] (1172)
234 HUANG Zheng-Feng, Chen Fan, Jiang Cui-Yun, Liang Hua-Guo
  A Hybrid Hardening Strategy for Circuit Soft-error-tolerance Based on Timing Priority
    JEIT   2014 Vol.36 (1): 234-240 [Abstract] (1179) [HTML 1 KB] [PDF 386 KB] (1000)
3011 Yang Yin-Tang, Wang Feng-Juan, Zhu Zhang-Ming, Liu Xiao-Xian, Ding Rui-Xue
  Analytical Model for Parasitic Capacitance of Tapered Through-silicon-vias with MOS Effect
    JEIT   2013 Vol.35 (12): 3011-3017 [Abstract] (1569) [HTML 1 KB] [PDF 282 KB] (1166)
3018 Zhang Chun-Hong, Yang Hai-Gang, Shi Chuan-Jin, Wei Yuan-Feng, Yu Le, Chen Zhu-Jia, Qu Xiao-Gang
  Dynamic Width Controller for Switch Mode DC-DC Converter
    JEIT   2013 Vol.35 (12): 3018-3023 [Abstract] (1169) [HTML 1 KB] [PDF 277 KB] (1117)
3024 Wu Rui-Zhen, Yang Yin-Tang, Zhang Li, Lu Feng-Lei
  A Two-level Arbitration Algorithm Based on Weight and Round-robin
    JEIT   2013 Vol.35 (12): 3024-3029 [Abstract] (1373) [HTML 1 KB] [PDF 253 KB] (1366)
2508 Wang Xian-Jian, Wang Lun-Yao, Chu Zhu-Fei, Xia Yin-Shui
  Nano-meter CMOS Circuit Cell Assignment Based on Pseudo-Boolean Satisfiability
    JEIT   2012 Vol.34 (10): 2508-2513 [Abstract] (1277) [HTML 1 KB] [PDF 262 KB] (664)
2247 Yu Le, Yang Hai-Gang, Xie Yuan-Lu, Zhang Jia, Zhang Chun-Hong, Wei Yuan-Feng
  A 3D IC Self-test and Recovery Method Based on Through Silicon Via Defect Modeling
    JEIT   2012 Vol.34 (9): 2247-2253 [Abstract] (1519) [HTML 1 KB] [PDF 460 KB] (1254)
2007 Xiang Qun-Liang, Zhang Pei-Yong, Ouyang-Dong-Sheng, Feng Chen-Hui
  Multiple Frequency Slots Based Physical Unclonable Functions
    JEIT   2012 Vol.34 (8): 2007-2012 [Abstract] (1451) [HTML 1 KB] [PDF 250 KB] (1541)
1012 Yang Yan-Fei, Yang Yin-Tang, Zhu Zhang-Ming, Zhou Duan
  Design of High-speed Asynchronous Pipeline Based on Parallel Completion Detection
    JEIT   2012 Vol.34 (4): 1012-1016 [Abstract] (1494) [HTML 1 KB] [PDF 262 KB] (743)
3035 Ruan Ying, Liu Yan-Hua, Chen Lei, Lai Zong-Sheng
  A 2.4 GHz Fully-integrated SiGe BiCMOS Power Amplifier
    JEIT   2011 Vol.33 (12): 3035-3039 [Abstract] (1937) [HTML 1 KB] [PDF 336 KB] (1200)
2500 Chen Xin, Wu Ning
  A Dynamic Bandwidth Control Algorithm for Digitally Controlled Phase-locked Loop
    JEIT   2011 Vol.33 (10): 2500-2505 [Abstract] (2174) [HTML 1 KB] [PDF 429 KB] (836)
2536 Shi Sheng-Qing, Chen Kai, Wang Yu, Luo Rong
  Node Importance Analysis in Complex Networks Based on Hardware Computing
    JEIT   2011 Vol.33 (10): 2536-2540 [Abstract] (2009) [HTML 1 KB] [PDF 288 KB] (867)
2237 Li Ya-Ni, Yang Yin-Tang, Zhu Zhang-Ming, Qiang Wei
  Design of Zero-crossing Distortion of Boost Power Factor Correction (PFC) Based on Feedforward Current Control Slope Compensation
    JEIT   2011 Vol.33 (9): 2237-2242 [Abstract] (2328) [HTML 1 KB] [PDF 680 KB] (2027)
First page | Prev page | Next page | Last pagePage 1 of 2, 49 records
     京ICP备05002787号

© 2010 JOURNAL OF ELECTRONICS & INFORMATION TECHNOLOGY
Institute of Electronics, Chinese Academy of Sciences, P.O.Box 2702, Beijing 100190
Tel: +86-10-58887066　Fax: +86-10- 58887539,Email: jeit@mail.ie.ac.cn

Supported by:Beijing Magtech