一种基于与非锥簇架构FPGA输入交叉互连设计优化方法

doi:10.11999/JEIT151216

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Abstract

In order to break through the bottleneck of the huge cluster area in AIC (And-Inverter Cone) architecture based FPGA, the research on the optimisation of the input crossbar architecture is carried on. A post-pack netlist statistics method is creatively proposed to analyze the utilization of AIC cluster inputs and feedbacks and to guide the input crossbar design. And on the architecture parameter design level, it is firstly proposed to separately design the connective probability of the AIC cluster inputs and feedbacks. Through substantial experiments, optimum connective probability combination is derived. From the circuit implement view, dual-phases multiplexer input crossbar is presented according to the characteristics of AIC. The area of the AIC cluster, optimized through the proposed approach, achieves 21.21% smaller than the original one, the huge area problem is markedly ameliorated. When implementing the MCNC and VTR benchmarks, compared to Stratix IV, LUT based FPGA from Altera, the area-delay product of the AIC FPGA after optimisation is reduced by 48.49% and 26.29%, respectively. Compared to the original AIC-based FPGA architecture, the area-delay product is reduced by 28.48% and 28.37%, respectively.

Key words： And-Inverter Cone (AIC) AIC cluster Post-pack netlist statistics Connective probability Separately design Dual-phases multiplexer input crossbar

Received: 28 October 2015 Published: 14 April 2016

PACS:

TN402

Fund:

The National Natural Science Foundation of China (61271149)

Corresponding Authors: YANG Haigang E-mail: yanghg@mail.ie.ac.cn

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	Articles by authors
	HUANG Zhihong
	LI Wei
	YANG Liqun
	JIANG Zhenghong
	WEI Xing
	LIN Yu
	YANG Haigang

Cite this article:

HUANG Zhihong,LI Wei,YANG Liqun等. An Input Crossbar Optimisation Method for And-inverter Cone Based FPGA[J]. JEIT, 2016, 38(9): 2397-2404.

URL:

http://jeit.ie.ac.cn/EN/10.11999/JEIT151216 OR http://jeit.ie.ac.cn/EN/Y2016/V38/I9/2397

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