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| A Mixed Method of Leakage Optimization for Gate-level Netlist |
| Shu Yi①② Cai Gang① Yang Hai-gang① |
①(Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China)
②(University of Chinese Academy of Sciences, Beijing 100049, China) |
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Abstract In deep-submicron Integrated Circuit (IC) design regime, the portion of leakage power consumption increases rapidly, therefore, leakage power optimization becomes a crucial part of circuit design flow. This paper proposes a mixed method of leakage optimization for gate-level netlist. The proposed method combines integer programming and heuristic algorithm to optimize leakage power at the cost of decreased timing slack. It starts at a given timing feasible design and finds alternative cell for each gate in the netlist with optimal power-delay sensitivity, then assigns alternative cell to individual gate during a levelized traverse on netlist according to specific rules. Finally, the proposed method performs a path-based timing recovery phase to fix timing violations. The entire flow iteratively converts timing slack to power-saving until no improvements could be gained. The benchmark results shows that our the proposed method achieves 10% on average, maximum 26% leakage power reduction while timing violation is confined within 5 ps.
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Received: 24 September 2013
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Corresponding Authors:
Yang Hai-gang
E-mail: yanghg@mail.ie.ac.cn
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2014, Vol. 36 
