|
|
|
| A Hybrid Hardening Strategy for Circuit Soft-error-tolerance Based on Timing Priority |
| Huang Zheng-feng① Chen Fan② Jiang Cui-yun③ Liang Hua-guo① |
①(School of Electronic Science & Applied Physics, Hefei University of Technology, Hefei 230009, China)
②(School of Computer & Information, Hefei University of Technology, Hefei 230009, China)
③(School of Mathematics, Hefei University of Technology, Hefei 230009, China) |
|
|
|
|
Abstract In order to reduce effectively the hardware and timing overhead for circuit soft-error-tolerance, a hybrid hardening technique for soft error tolerance is proposed based on timing priority in this paper. A two-stage hardening strategy is exploitsed by using flip-flop replacement and duplicated gate method to harden circuit. At first stage, based on the timing priority principle, high reliability temporal redundancy flip-flop is used to harden circuit on the path of timing slack. At second stage, duplicated gate method is used on timing sensitive path. Compared with traditional techniques, the proposed technique can not only mask the Single Event Transient (SET) and protect against the Single Event Upset (SEU), but also reduce the overhead of the area. The experiment result of ISCAS’89 benchmark circuits in 45 nm Nangate process proves that the circuit average soft error rate is reduced by more than 99% and the average area overhead is 36.84%.
|
|
Received: 07 April 2013
|
|
|
|
Corresponding Authors:
Chen Fan
E-mail: cf2008chenfan@163.com
|
|
|
|
|
|
|
2014, Vol. 36 
