动态自适应低密度奇偶校验码译码器的FPGA实现

doi:10.11999/JEIT141609

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Abstract

Faced with the complex environment of deep space communication, the adaptive capacity can have an impact on the ability of the Low Density Parity Check (LDPC) code decoder to maintain long-term stability. This paper proposes a design method of dynamic adaptive LDPC code decoder. Through the IP-based design of each function module, the design method of dynamic adaptive can be mapped to each function module in DVB-S2 LDPC code decoder. The verification results based on the Stratix IV FPGA show the dynamic adaptive LDPC code decoder not only can decode under the different code length and code rate, but also can decode under the different decoding performance. Meanwhile, the single-channel decoder can ensure the information throughput to reach to 40.9~71.7 Mbps.

Key words： Low Density Parity Check (LDPC) code decoder Dynamic adaptive DVB-S2 standard FPGA

Received: 15 December 2014 Published: 02 June 2015

PACS:	TN911.22
	TN402

Corresponding Authors: Yang Hai-gang E-mail: yanghg@mail.ie.ac.cn

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	Lan Ya-zhu
	Yang Hai-gang
	Lin Yu

Cite this article:

Lan Ya-zhu,Yang Hai-gang,Lin Yu. Design of Dynamic Adaptive LDPC Decoder Based on FPGA[J]. JEIT, 2015, 37(8): 1937-1943.

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http://jeit.ie.ac.cn/EN/10.11999/JEIT141609 OR http://jeit.ie.ac.cn/EN/Y2015/V37/I8/1937

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