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| Implementation of PCI Bus Multi-user Data Buffer Manager |
| Qiao Lu-feng①②; Wang Zhi-gong①; Huang Bin①; Lu Yuan-lin① |
| ①Institute of RF- & OE-ICs, Southeast University,Nanjing 210096, China;②Institute of Communication Engineering, Nanjing 210007, China |
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Abstract The circuit structure of a kind of PCI bus multi-user data Buffer Manager (BM) is analyzed in this paper, and typical simulating waveform is presented. The method to allocate the data buffers, port bandwidth, maximum user waiting time and minimum user buffer requirements are analyzed theoretically. The expression to calculate the minimum memory needed in the BM is given. Based on the analysis, a 128-user buffer manager is realized with XILINX XCV600EPQ240 and verified in application systems.
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Received: 27 February 2004
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2005, Vol. 27 
