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| The Research of Area-Efficiency for the Routing Channel Distribution in FPGAs |
| Xu Xin-min①; Wang Qian①; Yan Xiao-lang② |
①Institute of Electronic Circuit and Information System, Zhejiang University, Hangzhou 310027, China;
②Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China |
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Abstract The effect of track distribution on chip area is investigated in this paper. Several typical distributions in math (Gaussian, Sine and Trigonal) are introduced to realize FPGAs architectures with routing channel width varying randomly on software platform. These various kinds of FPGA architecture are made comparison to the traditional FPGA with uniform routing channel width. The key results are that the non-uniform routing architectures educed from the introduction of math’s distribution have a better area efficient than the uniform ones without sacrificing the circuit speed. And the trend of routing channel width transformation is that in the center of the chip is the peak point, and from the center to the edges the channel width becomes narrow gradually.
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Received: 17 February 2005
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| [1] |
LIANG Huaguo, SUN Hongyun, SUN Jun, HUANG Zhengfeng, XU Xiumin, YI Maoxiang, OUYANG Yiming, LU Yingchun, YAN Aibin. FPGA-based Soft Error Sensitivity Analysis Method for Microprocessor[J]. JEIT, 2017, 39(1): 245-249. |
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2006, Vol. 28 
