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| An Efficient Mixed-mode Test-Per-Clock Scheme |
| LIU Tieqiao NIU Xiaoyan YANG Jie MAO Feng |
| (Hangzhou Dianzi University, Hangzhou 310018, China) |
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Abstract A mixed-mode Test-Per-Clock Built In Self Test (BIST) scheme is proposed. The test consists of two parts: the free Linear Feedback Shift Register (LFSR) pseudo-random test mode and the deterministic test pattern based on controlled LFSR. Pseudo random test mode is used to quickly detect pseudo-random susceptible faults and reduce the deterministic data storage. Controlled LFSR test mode uses the control bits directly stored in the ROM to generate a deterministic test of the remaining faults. Based on the theoretical analysis of the proposed mixed-mode BIST test structure, a pseudo-random test sequence selection method and a deterministic test generation method based on controlled linear shifter are proposed. Simulation results on benchmark circuits show that the proposed method can obtain the complete single stuck-at fault coverage and has good stability in test generation. Compared with other methods, it has simpler Test Pattern Generator (TPG) design and lower test cost as well as shorter test application time.
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Received: 08 November 2016
Published: 11 May 2017
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| Fund:Zhejiang Provincial Natural Science Foundation (LQ15F040005) |
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Corresponding Authors:
LIU Tieqiao
E-mail: tieqiao120@163.com
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| [1] |
CHATTERJEE M and PRADHAN D K. A BIST pattern generator design for near-perfect fault coverage[J]. IEEE Transactions on Computers, 2003, 52(12): 1543-1558. doi: 10.1109/TC.2003.1252851.
|
| [2] |
LI L and MIN Y. An efficient BIST design using LFSR- ROM architecture[C]. 9th Asian Test Symposium, Taipei, 2000: 386-390.
|
| [3] |
FISER P and KUBATOVA H. An efficient mixed-mode BIST technique[C]. 7th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2004, Tatranská Lomnica, SK, 2004: 227-230.
|
| [4] |
JAS A, KRISHANA C V, and TOUBA N A. Weighted pseudo-random hybrid BIST[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004, 12(12): 1277-1283. doi: 10.1109/TVLSI.2004.837985.
|
| [5] |
WANG Seongmoon, WEI Wenlong, and WANG Zhanglei. A low overhead high test compression technique using pattern clustering with n-detection test support[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010, 18(12): 1672-1685. doi: 10.1109/TVLSI.2009.2026420.
|
| [6] |
KALLIGEROUS E, BAKALIS D, KAVOUSIANOS X, et al. Reseeding-based test set embedding with reduced test sequences[C]. International Symposium on Quality Electronic Design, San Jose, 2005: 226-231.
|
| [7] |
胡晨, 许舸夫, 张哲. 一种基于受控LFSR的内建自测试结构及其测试矢量生成[J]. 电路与系统学报, 2002, 7(3): 13-16.
|
|
HU Chen, XU Gefu, and ZHANG Zhe. A BIST structure and test pattern generation method based on controlled LFSR[J]. Journal of Circuits and Systems, 2002, 7(3): 13-16.
|
| [8] |
YOU Zhiqiang, WANG Weizheng, DOU Zhiping, et al. A scan disabling-based BAST scheme for test cost reduction[J]. IEICE Electronics Express, 2011, 8(16): 1367-1373.
|
| [9] |
ACEVEDO O and KAGARIS D. On the computation of LFSR characteristic polynomials for built-in deterministic test pattern generation[J]. IEEE Transactions on Computers, 2016, 65(2): 664-669. doi: 10.1109/TC.2015.2428697.
|
| [10] |
CHEN L, CUI Aijiao, and CHANG C H. Design of optimal scan tree based on compact test patterns for test time reduction[J]. IEEE Transactions on Computers, 64(12), 2015: 3417-3492. doi: 10.1109/TC.2015.2401019.
|
| [11] |
LIU T, KUANG J, YOU Z, et al. An effective deterministic test generation for test-per-clock testing[J]. IEEE Aerospace & Electronic Systems Magazine, 2014, 29(5): 25-33. doi: 10.1109/MAES.2014.130192.
|
| [12] |
MRUGALSKI G, RAJSKI J, SOLECKI J, et al. Test express -new time-effective scan-based deterministic test paradigm[C]. 2015 IEEE 24th Asian Test Symposium(ATS), Mumbai, 2015: 19-24.
|
| [13] |
RAJSKI J, SOLECKI J, TYSZER J, et al. Scan chain configuration for test-per-clock based on circuit topology[P]. US9009553, 2015.
|
| [14] |
SHIAO C M, LIEN W C, and LEE K J. A test-per-cycle BIST architecture with low area overhead and no storage requirement[C]. 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, 2016: 1-4.
|
| [15] |
NOVAK O and NOSEK J. Test-per-clock testing of the circuits with scan[C]. Proceedings Seventh International On-Line Testing Workshop, Giardini Naxos, Taormina, Italy, 2001: 90-92.
|
| [16] |
LEE H K and HA D S. Atalanta: An efficient ATPG for combinational circuits[R]. Technical Report, 93-12, Department of Electrical Engineering, Virginia Polytechnic Institute and State University, Blacksburg, Virginia, 1993.
|
| [17] |
LEE H K and HA D S. HOPE: An efficient parallel fault simulator for synchronous sequential circuits[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1996, 15(9): 1048-1058. doi: 10.1109/ 43.536711.
|
| [18] |
邝继顺, 周颖波, 蔡烁. 一种用于测试数据压缩的自适应EFDR编码方法[J]. 电子与信息学报, 2015, 37(10): 2529-2535. doi: 10.11999/JEIT150177.
|
|
KUANG Jishun, ZHOU Yingbo and CAI Shuo. Adaptive EFDR coding method for test data compression[J]. Journal of Electronics & Information Technology, 2015, 37(10): 2529-2535. doi: 10.11999/JEIT150177.
|
| [19] |
KUANG J, ZHANG L, YOU Z, et al. Improve the compression ratios for code-based test vector compressions by decomposing[C]. 20th IEEE European Test Symposium (ETS), Cluj-Napoca, 2015: 1-6.
|
|
|
|
