可重构非线性布尔函数利用率模型研究与硬件设计

doi:10.11999/JEIT160733

Abstract
Figure/Table
References (20)
Related Citation (15)

Download: PDF (665 KB)
Export: BibTeX | EndNote (RIS)

Abstract

In order to solve the problem that the Non-Linear Boolean Function (NLBF) unit in sequence cryptogram possesses poor hardware resource utilization, the utilization model of basic component composed by Look-Up Table (LUT) is studied and three essential parameters (LUT size, cluster scale and the number of input ports) which impact hardware utilization are decided combined with the early processing results of adaption algorithm. On the basis, the mapping of NLBF limited to variable frequency is realized and the design of nonlinear computing unit is implemented, which can support multi-way parallel processing. The circuit is developed and synthesized in SMIC 180 nm. Its working frequency realizes 241 MHz and it achieves the maximum throughput of 7.71 Gb/s in parallelism of 32. The results after evaluating the utilization of various NLBFs show that all utilization can reach over 91.14% and the utilization increases continually as the parallelism increases.

Key words： Sequence cryptogram Reconfigurable computing Non-Linear Boolean Function (NLBF) Look-Up Table (LUT)

Received: 08 July 2016 Published: 09 February 2017

PACS:	TN918
	TP311

Fund:

The National Natural Science Foundation of China (61404175)

Corresponding Authors: LI Wei E-mail: liwei12@fudan.edu.cn

	Service

	E-mail this article
	Add to my bookshelf
	Add to citation manager
	E-mail Alert
	RSS
	Articles by authors
	DAI Zibin
	WANG Zhouchuang
	LI Wei
	LI Jiamin
	Nan Longmei

Cite this article:

DAI Zibin,WANG Zhouchuang,LI Wei等. Hardware Implementation and Utilization Model Research for Reconfigurable Non-linear Boolean Function[J]. JEIT, 2017, 39(5): 1226-1232.

URL:

http://jeit.ie.ac.cn/EN/10.11999/JEIT160733 OR http://jeit.ie.ac.cn/EN/Y2017/V39/I5/1226

[1]	ZENG G, DONG X, and BORNEMANN J. Reconfigurable feedback shift register based stream cipher for wireless sensor networks[J]. IEEE Wireless Communications Letters, 2013, 2(5): 559-562. doi: 10.1109/wcl.2013.13.130292.
[2]	禹思敏, 吕金虎, 李澄清. 混沌密码及其在保密通信中应用的进展[J]. 电子与信息学报, 2016, 38(3): 735-752. doi: 10.11999 /JEIT151356.
	YU Simin, LU Jinhu, and LI Chengqing. Some progresses of chaotic cipher and its application in multimedia secure communications[J]. Journal of Electranics & Information Technology, 2016, 38(3): 735-752. doi: 10.11999/JEIT151356.
[3]	丁群, 彭喜元, 杨自恒. 基于神经网络算法的组合序列密码芯片[J]. 电子学报, 2006, 34(3): 409-412. doi: 10.3321/j.issn: 0372-2112.2006.03.006.
	DING Qun, PENG Xiyuan, and YANG Ziheng. The cipher chip of combining stream based on the neural network algorithm[J]. Acta Electronica Sinica, 2006, 34(3): 409-412. doi: 10.3321/j.issn:0372-2112.2006.03.006.
[4]	MIKE H and JAY S. Improving FPGA performance and area using an adaptive logic module[J]. Leuven Belgium, Spring Berlin Heidelberg, 2004, 32(03): 135-144. doi: 10.1007/ 978-3-540-30117-2_16.
[5]	ANDERSON J H and QIANG W. Area-efficient FPGA logic elements: Architecture and synthesis[C]. 16th Asia and South Pacific Design Automation Conference, Yokohama, 2011: 369-375. doi: 10.1109/aspdac.2011.5722215.
[6]	陈韬, 杨萱, 戴紫彬, 等. 面向序列密码的非线性反馈移位寄存器可重构并行化设计[J]. 上海交通大学学报, 2013, 47(1): 28-32.
	CHEN Tao, YANG Xuan, DAI Zibin, et al. Design of a reconfigurable parallel nonlinear feedback shift register structure targeted at stream cipher[J]. Journal of Shanghai Jiao Tong University, 2013, 47(1): 28-32.
[7]	SATWANT S, JONATHAN R, PAUL C, et al. The effect of logic block architecture on FPGA performance[J]. IEEE Journal of Solid-State Circuits, 1992, 27(3): 281-287. doi: 10.1109/4.121549.
[8]	ELIAS A and JONATHAN R. The effect of LUT and cluster size on deep-submicron FPGA performance and density[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004, 12(3): 288-298. doi: 10.1109/tvlsi.2004. 824300.
[9]	KUON L and JONATHAN R. Measuring the gap between FPGAs and ASICs[C]. Acm/sigda International Symposium on Field Programmable Gate Arrays, Monterey, 2015: 21-30. doi: 10.1145/1116201.1117205.
[10]	MANA P, TALATI N, RISWADKAR A, et al. Stateful-NOR based reconfigurable architecture for logic implementation[J]. Microelectronics Journal, 2015, 46(6): 551-562. doi: 10.1016/ j.mejo.2015.03.021.
[11]	TANG X and WANG L. The effect of LUT size on nanometer FPGA architecture[C]. IEEE 11th International on Solid-State and Integrated Circuit Technology, Xi’an, 2012: 1-4. doi: 10.1109/icsict.2012.6467767.
[12]	DICKIN D and SHANNON L. Exploring FPGA technology mapping for fracturable LUT minimization[C]. International Conference on Field-Programmable Technology, New Delhi, 2011: 1-8. doi: 10.1109/fpt.2011.6132691.
[13]	FAROOQ U and ASLAM M. Design and implementation of basic building blocks of FPGA using memristor-transistor hybrid approach[C]. 2015 Fifth International Conference on Innovative Computing Technology, Vigo, 2015: 142-147. doi: 10.1109/intch.2015.7173484.
[14]	ASLAM M H, FAROOQ U, AWAIS M, et al. Exploring the effect of LUT size on the area and power consumption of a novel memristor-transistor hybrid FPGA architecture[J]. Arabian Journal for Science & Engineering, 2016, 41(8): 3035-3049. doi: 10.1007/s13369-016-2068-8.
[15]	TANG Xifan and DE-MICHELI G. Pattern-based FPGA logic block and clustering algorithm[P]. US, 20160063168. 2016. doi: 10.1109/fpl.2014.6927429.
[16]	SAXENA S and TIWARI A. A comparative study of leakage reduction techniques used in, FGPA for optimized area and power consumption[J]. International Journal of Engineering Research & Applications, 2014, 4(2): 89-94.
[17]	王周闯, 戴紫彬, 李伟. 高效适配NLBF序列密码的全局定向搜索算法[J]. 计算机应用, 2016, 36(9): 65-69. doi: 10.11772/ j.issn 1001-9081.2016.09.
	WANG Zhouchuang, DAI Zibin, and LI Wei. Global directional search algorithm adapting NLBF sequence cryptogram efficiently[J]. Journal of Computer Applications, 2016, 36(9): 65-69. doi: 10.11772/j.issn 1001-9081.2016.09.
[18]	秦晓懿, 王瀚晟, 曾烈光. 线性和非线性寄存器系统的并行化技术[J]. 电子学报, 2003, 31(3): 406-410. doi: 10.3321/j.issn: 0372-2112.2003.03.023.
	QIN Xiaoyi, WANG Hansheng, and ZENG Lieguang. Paralleling techniques for linear and nonlinear register systems[J]. Acta Electronica Sinica, 2003, 31(3): 406-410. doi: 10.3321/j.issn:0372-2112.2003.03.023.
[19]	李伟. 面向序列密码的反馈移位寄存器可重构并行化设计技术研究[D]. [硕士论文], 解放军信息工程大学, 2009.
	LI Wei. Research on technology of reconfigurable parallel feedback shift register targeted at stream cipher[D]. [Master dissertation], PLA Information Engineering University, 2009.
[20]	REBEIRO C and MUKHOPADHYAY D. High speed compact elliptic curve cryptoprocessor for FPGA platforms [C]. International Conference Progress in Cryptology- Indocrypt 2008, Kharagpur, 2008: 376-388. doi: 10.1007/978- 3-540-89754-5_29.