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| Leakage Current Optimization for FPGA Switch Matrixes Based on Routing Architecture |
| Wang Yi①② Yang Hai-gang① Yu Le①② Sun Jia-bin① |
①(Institute of Electronics, Chinese Academy of Sciences, Beijing 100190, China)
②(University of Chinese Academy of Sciences, Beijing 100049, China) |
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Abstract From the perspective of routing architecture, a leakage reduction method of switch matrixes in FPGA is proposed. Based on the conclusion of state-dependent leakage, the lowest leakage current of switch matrixes in FPGA is equivalently computed in a small size of matrix cell using the transition property of SWitch Box (SWB). Because the presented algorithm could research the lowest leakage state in finite SWB output state combinations, rather than confirming SWB output state by level-restoring circuit, the algorithm is used for efficient reduction of leakage in switch matrixes and is compatible with the optimization of leakage at the circuit-level.
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Received: 01 March 2013
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Corresponding Authors:
Yang Hai-gang
E-mail: yanghg@mail.ie.ac.cn
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LIANG Huaguo, SUN Hongyun, SUN Jun, HUANG Zhengfeng, XU Xiumin, YI Maoxiang, OUYANG Yiming, LU Yingchun, YAN Aibin. FPGA-based Soft Error Sensitivity Analysis Method for Microprocessor[J]. JEIT, 2017, 39(1): 245-249. |
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2013, Vol. 35 
