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| An Optimized Bus Scheduling Scheme Based on Specific Application |
| Li De-xian; Peng Jian-ying; Yan Xiao-lang |
| Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China |
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Abstract An application-specific bus scheduling scheme was proposed in this paper. Two-fold optimization was considered in this scheme based on the communication events collected by system modeling and simulation. The first one, which had higher priority, was real time constraints of tasks while the other was making use of bus idle time to transfer data as much as possible. A configurable optimization parameter α was also proposed for the tradeoff between the total bus time consumed and the extra on-chip buffer requirements. This scheme was implemented in a dual-core SoC (System on Chip) for the H.264/AVC decoder and compared with RR (Round Robin), FP (Fixed Priority) and SBA (Slack Based Arbitration) schemes. The results showed that the proposed scheme had an average 16.6%, 13.2% and 9.7% less bus time when α was set to 0.5. The number of missed real time constraints tasks was 59.4% less than the SBA scheme, which was the closest to our scheme. The relationship between α and the extra on-chip buffer cost showed that under worst condition (α=0), it was only 435 bytes.
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Received: 30 January 2008
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2009, Vol. 31 
