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Research on SPM’s Energy Model for Low Power Compilation |
Jiang Xiang-tao; Hu Zhi-gang; He Jian-biao |
School of Information Science and Engineering, Central South University, Changsha 410083, China |
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Abstract In order to achieve a better application effect of Scratch-Pad Memory(SPM), it,s appropriate to construct a proper SPM’s performance and power-consumption model to guide the compiling optimization process. The existing power-consumption modeling can only provide SPM,s average access power-consumption which didn’t reflect the characteristic that the actual circuit’s power-consumption varied as the input varied. It restricts further optimization. This thesis proposes to construct SPM’s basic power-consumption modeling according to the circuit structure and generate modeling,s parameters based on program,s runtime information. These can reflect the circuit’s actual active degree when different programs executed. Shown in the experiment, the power-consumption measured is basically as accurate as the one that based on the existing statistical method on average. Furthermore, the new modeling can reflect the difference of power-consumption when different programs access SPM. This technique has an important guiding significance to the access mode as the compliers optimize SPM.
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Received: 17 January 2008
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