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| VLSI Design of the Low-Power Rake Receiver for Wireless Sensor Networks |
| Quan Yuan-yuan①; Wang Pei②; He Hong-lu①; Yuan Xiao-bing①; Zhu Ming-hua① |
| ①Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China;②Mathematics & Science College, Shanghai Normal University, Shanghai 200234, China |
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Abstract A low-power VLSI Rake receiver is proposed and realized on FPGA for wireless sensor networks used in complicated wireless environments. Low-power design strategies including reducing clock frequency, sharing of models and dynamic sleeping control are used to reduce the power consumption in order to fit the energy limitations in wireless sensor networks. Simulations and applications show that the receiver can specially reduce VLSI resource and power consumption compared to ordinary Rake receiver.
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Received: 30 December 2006
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2008, Vol. 30 
