Design of a Low-spur Charge Pump for High Performance CMOS Phase-locked Loops
SHI Zhan① YU Jun① TANG Zhen’an① CAI Hong① FENG Chong①②
①(School of Electronic Science and Technology, Dalian University of Technology, Dalian 116024, China) ②(College of Information & Communication Engineering, Dalian Minzu University, Dalian 116600, China)
On the basis of the analysis of the structure, operation principle and mechanism of generating spurs of the charge pump, a charge pump with a low static current mismatch and a low timing mismatch is proposed. This charge pump suppresses the jitter and spurs in high-speed Phase-Looked Loops (PLL) by improving the timing mismatch and the current mismatch during switching in the charge pump. Based on the SMIC 0.18 μm CMOS radio frequency technology with 1.8 V power supply, the phase noise simulation of the PLLs adopting the proposed charge pump is performed. The simulation results demonstrate that those PLLs achieve a low noise performance: the second-order PLL shows a period jitter of 1.05 ps and the largest reference spur of -121 dBc with the PLL output frequency of 480 MHz.
HUANG Shuilong and WANG Zhihua. An adaptive PLL architecture to achieve fast settling time[J]. Journal of Electronics & Information Technology, 2007, 29(6): 1492-1495.
LI Xuechu, GAO Qingyun, CHEN Haoqiong, et al. The design of monolithic CMOS clock recovery circuit[J]. Journal of Electronics & Information Technology, 2007, 29(6): 1496-1499.
[3]
LIU L and POKHAREL R. Compact modeling of phase-locked loop frequency synthesizer for transient phase noise and jitter simulation[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, 35(1): 166-170. doi: 10.1109/TCAD.2015.2472018.
[4]
GIERKINK S L J. Low-spur, low-phase-noise clock multiplier based on a combination of PLL and recirculating DLL with dual-pulse ring oscillator and self-correcting charge pump[J]. IEEE Journal of Solid-State Circuits, 2008, 43(12): 2967-2976. doi: 10.1109/JSSC.2008.2006225.
[5]
KIM N S and RABAEY J M. A 3~10mW, 3.1~10.6 GHz integer-N QPLL with reference spur reduction technique for UWB-based cognitive radios[C]. Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Phoenix, AZ, 2015: 67-70. doi: 10.1109/RFIC.2015.7337706.
[6]
BANERJEE D. PLL Performance, Simulation and Design[M]. Texas: Dog Ear Publishing, 2006: 64-65.
CHEN Yongcong. Design technique to restrain reference spurs in CMOS phase lock loops[J]. Journal of Semiconductors, 2006, 27(12): 2196-2202.
[8]
RHEE W. Design of high-performance CMOS charge pumps in phase-locked loops[C]. Proceedings of the IEEE Circuits and Systems, Orlando, FL, 1999, 2: 545-548. doi: 10.1109/ ISCAS.1999.780807.
[9]
MANIKANDAN R R and AMRUTUR B. A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs[J]. Microelectronics Journal, 2015, 46(6): 422-430. doi: 10.1016/j.mejo.2015.03.004.
[10]
ZHANG Z, YANG J, LIU L, et al. Source-switched charge pump with reverse leakage compensation technique for spur reduction of wideband PLL[J]. Electronics Letters, 2016, 52(14): 1211-1212. doi: 10.1049/el.2016.1036.
[11]
LI S, JIANG J, ZHOU X, et al. A low phase noise and low spur PLL frequency synthesizer for GNSS receivers[J]. Journal of Semiconductors, 2014, 35(1): 96-103. doi: 10.1088/1674-4926/35/1/015004.
[12]
LOZADA O and ESPINOSA G. A charge pump with a 0.32% of current mismatch for a high speed PLL[J]. Analog Integrated Circuits & Signal Processing, 2015, 86(2): 321-326. doi: 10.1007/s10470-015-0676-y.
XUE Hong, LI Zhiqun, WANG Zhigong, et al. A charge pump design for low-spur PLL[J]. Journal of Semiconductors, 2007, 28(12): 1988-1992.
[14]
CHOI Y S and HAN D H. Gain-boosting charge pump for current matching in phase-locked loop[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2006, 53(10): 1022-1025.
[15]
GUPTA S, MONDAL S A, and RAHAMAN H. Charge pump circuit with improved absolute current deviation and increased dynamic output voltage range across PVT variations[C]. Proceedings of the 2015 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), Hyderabad, 2015: 32-35. doi: 10.1109/PrimeAsia.2015.7450465.
[16]
MOON J W, CHOI K C, and CHOI W Y. A 0.4-V, 90～350-MHz PLL with an active loop-filter charge pump[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2014, 61(5): 319-323. doi: 10.1109/TCSII.2014. 2312800.
[17]
WANG S F, HWANG T S, and WANG J J. Phase-locked loop design with fast-digital-calibration charge pump[J]. International Journal of Electronics, 2015, 103(2): 1-13. doi: 10.1080/00207217.2015.1036371.
[18]
MANEATIS J G. Low-jitter process-independent DLL and PLL based on self-biased techniques[J]. IEEE Journal of Solid-State Circuits, 1996, 31(11): 1723-1732.
[19]
MANEATIS J G, KIM J, MCCLATCHIE I, et al. Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL[J]. IEEE Journal of Solid-State Circuits, 2003, 38(11): 1795-1803. doi: 10.1109/JSSC.2003.818298.
[20]
KIM S H and CHO S B. Low phase noise and fast locking PLL frequency synthesizer for a 915 MHz ISM band[C]. Proceedings of the 2007 International Symposium on Integrated Circuits, Singapore, 2007: 592-595.
[21]
CHU A, DEO N, AHMAD W, et al. An ultra-low power charge-pump PLL with high temperature stability in 130 nm CMOS[C]. Proceedings of the IEEE New Circuits and Systems Conference, Grenoble, 2015: 1-4. doi: 10.1109/ NEWCAS.2015.7182075.
[22]
MENG X and LIN F. Clock generator IP design in 180 nm CMOS technology[J]. Analog Integrated Circuits & Signal Processing, 2016, 87(3): 1-9. doi: 10.1007/s10470-016-0737-x.
[23]
THIBIEROZ H. Using spectre RF noise-aware PLL methodology to predict PLL behavior accurately[OL]. https://zh.scribd.com/document/67585642/Using-Spectre-RF-Noise-Aware-PLL-Methodology-to-Predict-PLL-Behavior-Accurately, 2007.
ZHANG Changming, XIAO Zhenyu, Zeng Lieguang, et al. Performance analysis of Single-Carrier (SC) 60 GHz communication system based on IEEE 802.11ad standard[J]. Journal of Electronics & Information Technology, 2012, 34(1): 218-222. doi: 10.3724/SP.J.1146.2011.00447.
MA Xiaohui and ZOU Chuanyun. Power spectral density of digital ultra wide-band signals[J]. Journal of Electronics & Information Technology, 2007, 29(8): 1877-1881.
