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The Design of DPLL for Low SNR Signals with Large Frequency Offset |
Shuai Tao;Liu HuiJie;Liang XuWen;Yang GenQing |
Micro-satellite State Key Joint Laboratory, Chinese Academy of Sciences, Shanghai 200050, China |
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Abstract The digital phase-locked loops design is a key technology for carrier and bit synchronization in coherent demodulation digital receiver. Large frequency offset and low SNR add more difficulties of the loop design from two different ways. Based on this condition, aim at fast acquisition and tracking, a method of digital loop parameter algorithm is proposed in this paper and some useful conclusions are given.
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Received: 15 March 2004
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