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Optimization Design of Digital Quadrature Demodulation Receiver Based on FPGA |
Qiu Zhao-kun; Ma Yun; Wang Wei; Chen Zeng-ping |
ATR Lab, National Univ. of Defense Technology, Changsha 410073, China |
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Abstract Under certain conditions, combining the polyphase filtering structure of decimation filter, put forward an optimum design method of quadrature demodulation receiver, which owns decimation structure. With the same number of multipliers in FPGA, the order of FIR filter in receiver with above optimum structure is nearly 4 times than it implemented in direct way. Finally the design instance is given.
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Received: 17 June 2004
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[1] |
LIANG Huaguo, SUN Hongyun, SUN Jun, HUANG Zhengfeng, XU Xiumin, YI Maoxiang, OUYANG Yiming, LU Yingchun, YAN Aibin. FPGA-based Soft Error Sensitivity Analysis Method for Microprocessor[J]. JEIT, 2017, 39(1): 245-249. |
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