PMOS晶体管工艺参数变化对SRAM单元翻转恢复效应影响的研究

doi:10.11999/JEIT170547

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Abstract Based on Synopsys TCAD 3-D device simulation, the effects of PMOS transistor process parameters on the upset and recovery effect of Static Random Access Memory (SRAM) memory cell are studied in a 65-nm bulk CMOS technology, mainly by changing the three process parameters. The simulation results show that reducing the doping concentration of deep-P⁺-well, N-well and threshold doping concentration in PMOS transistor can decrease the Linear Energy Transfer (LET) value of the upset and recovery. By reducing the doping concentration of deep-P⁺-well and N-well in PMOS transistor, the time of the upset and recovery increases. The conclusion of this paper is helpful to optimize the design of Static Random Access Memory cell mitigating Single-Event Effect (SEE), and can gives a great guidance for the anti-radiation integrated circuit under bulk CMOS process.

Key words： Static Random Access Memory (SRAM) Linear Energy Transfer (LET) value Time of the upset and recovery Single-Event Effect (SEE)

Received: 08 June 2017 Published: 14 September 2017

PACS:

TN432

Fund:The National Natural Science Foundation of China (61674002, 61474001, 61574001)

Corresponding Authors: WU Xiulong E-mail: xiulong@ahu.edu.cn

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	ZHANG Jingbo
	YANG Zhiping
	PENG Chunyu
	DING Penghui
	WU Xiulong

Cite this article:

ZHANG Jingbo,YANG Zhiping,PENG Chunyu等. Study on the Effect of Upset and Recovery for SRAM Under the Varying Parameters of PMOS Transistor[J]. JEIT, 2017, 39(11): 2755-2762.

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http://jeit.ie.ac.cn/EN/10.11999/JEIT170547 OR http://jeit.ie.ac.cn/EN/Y2017/V39/I11/2755

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