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Wide-width Bit Permutation Instructions for Accelerating Cryptographic Algorithms |
DAI Zibin① MA Chao① LI Wei② NAN Longmei② |
①(The PLA Information Engineering University, Zhengzhou 450001, China)
②(State Key Laboratory of ASIC and System, Fudan University, Shanghai 200433, China) |
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Abstract Wide-width bit permutation is a very commonly used operation in symmetric cryptographic algorithms. However, current word-oriented general microprocessors are inefficient to cope with the complex bit-level permutation operations. To solve this problem, two schemes for 2N-2N and kN-kN permutations are proposed respectively, including two extended instructions BEX and BEX-ROT. Furthermore, the efficient hardware implementation of the instructions are studied, and then a unified hardware circuit named RERS (Reconfigurable Extract and Rotation Shifter) is proposed with a corresponding reconfigurable routing algorithm. The RERS can share hardware resources to achieve the purpose of reducing area. The experimental results show that the proposed schemes can truly decrease the number of instructions for accomplishing an arbitrary wide-width bit permutation (instructions reduced by 10 times), which greatly accelerate the performance of microprocessors. At the same time, the overhead of hardware resources and delay caused by the two extended instructions is very low, which will not affect the normal operating frequency of the original microprocessors.
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Received: 25 November 2016
Published: 30 June 2017
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Fund:The National Natural Science Foundation of China (61404175) |
Corresponding Authors:
MA Chao
E-mail: wenlu_ma@163.com
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