基于数字锁相环的星载光谱仪本地时钟源设计

doi:10.11999/JEIT170088

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Abstract Under the condition of working in sun-synchronous orbit, the error correction strategy is put forward due to the error caused by the communication error. According to the complementary error characteristics between satellite clock and local clock, a Digital Phase Locked Loop (DPLL) is designed, which is applied to the low frequency input signal and the large frequency multiplication factor. The local clock tracks the satellite clock pulse phase fluctuations and eliminates the accumulate error constantly. The complete design is developed with Field Programmable Gate Array (FPGA) devices and the detailed theoretical analysis and experimental results are presented. Experiments show that the design of the clock source can correct the abnormal flip or lose of second pulse and jump or lose of broadcast time package constantly. It can enter the lock state in 5 input clock cycles, and the cumulative error is less than 100 μs. It can be used as the local clock source of satellite borne equipment.

Key words： Digital Phase Locked Loop (DPLL) Feedback control Proportional integral control Frequency- multiplier FPGA

Received: 23 January 2017 Published: 27 June 2017

PACS:

TN911.8

Fund:The National Natural Science Foundation of China (41275037), Anhui Province Outstanding Youth Science Foundation (1308085JGD03)

Corresponding Authors: WANG Yu E-mail: yuwang@aiofm.ac.cn

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	TIAN Yuze
	WANG Yu
	DAI Haishan
	FANG Hua
	LIU Wenqing

Cite this article:

TIAN Yuze,WANG Yu,DAI Haishan等. Design of Local Clock Source of Satellite Borne Spectrometer Based on Digital Phase Locked Loop[J]. JEIT, 2017, 39(10): 2397-2403.

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http://jeit.ie.ac.cn/EN/10.11999/JEIT170088 OR http://jeit.ie.ac.cn/EN/Y2017/V39/I10/2397

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