40 nm CMOS工艺下的低功耗容软错误锁存器

doi:10.11999/JEIT160889

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Abstract

To reduce the soft error rate of the circuit, this paper proposes a low power soft error tolerant latch based on time redundancy technology. The proposed latch can fully tolerate the Single Event Upset (SEU) when particles strike on internal nodes. Furthermore, it can efficiently mask the input Single Event Transient (SET). Its output node will not enter a high impedance state when a particle strikes on internal nodes, so the proposed latch can be applied to clock-gating circuits. Detailed SPICE simulations are done to evaluate the proposed latch circuit and previous latch circuits designed in the literatures. Compared with other soft error tolerant latches, the proposed latch introduces 13.4% delay overhead on average. While it can achieve 44.3% increase in filterable SET pulse width, 48.5% reduction in power, 46.0% reduction in Power Delay Product (PDP), and 9.1% reduction in transistor numbers on average.

Key words： Soft error Single Event Upset (SEU) Single Event Transient (SET) Hardened latch

Received: 02 September 2016 Published: 06 April 2017

PACS:

TN432

Fund:

The National Natural Science Foundation of China (61574052, 61371025, 61474036, 61674048), The Natural Science Foundation of Anhui Province (1608085MF149)

Corresponding Authors: LIANG Huaguo E-mail: huagulg@hfut.edu.cn

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	HUANG Zhengfeng
	WANG Shichao
	OUYANG Yiming
	YI Maoxiang
	LIANG Huaguo

Cite this article:

HUANG Zhengfeng,WANG Shichao,OUYANG Yiming等. Low Power Soft Error Tolerant Latch for 40 nm CMOS Technology[J]. JEIT, 2017, 39(6): 1464-1471.

URL:

http://jeit.ie.ac.cn/EN/10.11999/JEIT160889 OR http://jeit.ie.ac.cn/EN/Y2017/V39/I6/1464

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