一种基于FPGA的微处理器软错误敏感性分析方法

doi:10.11999/JEIT160225

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Abstract

In order to quickly and automatically analyze the soft error sensitivity for microprocessors, a soft error sensitivity analysis method using FPGA-based fault injection is proposed. The fault and fault-free microprocessors on a FPGA are board run simultaneously. Moreover, a fault injection controller, a fault classification module and a fault list module are also implemented on the hardware. The method inherits the parallelism of the FPGA and achieves a fast and automatical fault injection for all storage bits. Further, using a PIC16F54 microprocessor as experimental subject, approximate 300, 000 soft errors are injected into the microprocessors to analyze its soft error sensitivity. In order to demonstrate the sensitivity evaluation efficiency of the method, the quite sensitive storage cells are hardened and the sensitivity is analyzed again. Compared to the simulation approach, experimental results show that the proposed technique achieves four orders of magnitude speedup.

Key words： FPGA Fault injection Single event upset Soft error Sensitivity analysis

Received: 11 March 2016 Published: 09 October 2016

PACS:

TP302.8

Fund:

The National Natural Science Foundation of China (61274036, 61371025, 61474036, 61574052), Anhui Provincial Natural Science Foundation (1608085MF149)

Corresponding Authors: HUANG Zhengfeng E-mail: huangzhengfeng@139.com

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	Articles by authors
	LIANG Huaguo
	SUN Hongyun
	SUN Jun
	HUANG Zhengfeng
	XU Xiumin
	YI Maoxiang
	OUYANG Yiming
	LU Yingchun
	YAN Aibin

Cite this article:

LIANG Huaguo,SUN Hongyun,SUN Jun等. FPGA-based Soft Error Sensitivity Analysis Method for Microprocessor[J]. JEIT, 2017, 39(1): 245-249.

URL:

http://jeit.ie.ac.cn/EN/10.11999/JEIT160225 OR http://jeit.ie.ac.cn/EN/Y2017/V39/I1/245

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