高效低功耗低并行度LDPC编码方法

doi:10.11999/JEIT151362

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Abstract

Low-density parity-check code is the one of error-correction codes most approaching Shannon limit, which is adopted as a standard for channel coding by many international communication standard organizations. CCSDS recommends LDPC as channel coding scheme in near earth space and deep space communication. An efficient LDPC coding scheme with low power and low parallel is presented in this paper. By filling “0” and changing the cyclic-matrix structure, the proposed scheme implements a low parallel coding for the LDPC, which is recommended by CCSDS, and of which the size of submatrix of check matrices is odd. By analyzing the coding process, the valid bit “1” among input information bits is coded only, and it decreases obviously the code power. The encoder architecture for 7/8 LDPC is implemented in FPGA. The result shows that encoder achieves a high encoding speed approaching low parallel encoder scheme and a much lower encoding power while increases few hardware overhead.

Key words： Error-correction codes Low parallel Low power QC-LDPC VLSI design

Received: 03 December 2015 Published: 04 July 2016

PACS:

TN911.22

Corresponding Authors: YAN Wei E-mail: yanwei_nssc@163.com

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	YAN Wei
	XUE Changbin

Cite this article:

YAN Wei,XUE Changbin. An Efficient LDPC Encoder Scheme with Low-power Low-parallel[J]. JEIT, 2016, 38(9): 2268-2273.

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http://jeit.ie.ac.cn/EN/10.11999/JEIT151362 OR http://jeit.ie.ac.cn/EN/Y2016/V38/I9/2268

[1]	GALLAGER R G. Low-density parity-check codes[J]. IRE Transactions on Information Theory, 1962, 8(1): 21-28. doi: 10.1109/TIT.1962.1057683.
[2]	袁东风, 张海刚. LDPC码理论与应用[M]. 北京: 人民邮电出版社, 2008: 20-25.
	YUAN Dongfeng and ZHANG Haigang. LDPC Code Theory and Applications[M]. Beijing: Post and Telecom Press, 2008: 20-25.
[3]	MACKAY D C. Good error-correcting codes based on very sparse matrices[J]. IEEE Transactions on Information Theory, 1999, 45(2): 399-431. doi: 10.1109/18.748992.
[4]	CHUNG S Y. On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit[J]. IEEE Communications Letters, 2001, 5(2): 58-60. doi: 10.1109/ 4234.905935.
[5]	MAHDI A and PALIOURAS V. A low complexity-high throughput QC-LDPC encoder[J]. IEEE Transactions on Signal Process, 2014, 62(10): 2696-2708. doi: 10.1109/tsp. 2014.2314435.
[6]	栾志斌, 裴玉奎, 葛宁. 低存储高速可重构LDPC码译码器设计及ASIC实现[J]. 电子与信息学报, 2014, 36(10): 2287-2292. doi: 10.3724/SP.J.1146.2013.01939.
	LUAN Zhibin, PEI Yukui, and GE Ning. Design and ASIC implementation of low memory high throughput reconfigurable LDPC decoder[J]. Journal of Electronics & Information Technology, 2014, 36(10): 2287-2292. doi: 10.3724/SP.J.1146.2013.01939.
[7]	苏和光, 夏树涛. 一种新的码率兼容LDPC码打孔方案[J]. 电子与信息学报, 2011, 33(10): 2334-2339. doi: 10.3724/SP.J. 1146.2010.01202.
	SU Heguang and XIA Shutao. A novel puncturing scheme for rate-compatible LDPC codes[J]. Journal of Electronics & Information Technology, 2011, 33(10): 2334-2339. doi: 10. 3724/SP.J.1146.2010.01202.
[8]	CCSDS. CCSDS 131.0-B-2-TM synchronization and channel coding[S]. Washington, DC, USA, 2011.
[9]	CCSDS. CCSDS 131.1-O-2-low density parity check codes for use in near-earth and deep space applications[R]. Washington, DC, USA, 2007.
[10]	CCSDS. CCSDS 230.2-G-1-next generation uplink[R]. Washington, DC, USA, 2014.
[11]	CCSDS. CCSDS 231.1-O-1-short block length LDPC codes for TC synchronization and channel coding[R]. Washington, DC, USA, 2015.
[12]	张浩, 殷柳国. 星地高速数传系统LDPC编码器ASIC集成芯片设计[J]. 宇航学报, 2015, 36(1): 96-102.
	ZHANG Hao and YIN Liuguo. ASIC design of an LDPC encoder for satellite-ground high-speed data transmission system[J]. Journal of Astronautics, 2015, 36(1): 96-102.
[13]	燕威, 杨双, 薛长斌. 一种CCSDS标准低并行度高速LDPC编码方案[R]. 中国科学院国家空间科学中心, 2015.
	YAN Wei, YANG Shuang, and XUE Changbin. An encoder architecture scheme with low parallel and high speed for LDPC codes based CCSDS standard[R]. National Space Science Center, Chinese Academy of Science, 2015.
[14]	MCGUIRE M, SIMA M, and MILLER S. VLSI implementation of a shift-enabled reconfigurable array[C]. 2008 IEEE International Symposium on Circuits and Systems, 2008, 1(10): 1360-1363.
[15]	PARHI K K and OH D. Area efficient controller design of barrel shifters for reconfigurable LDPC decoders[C]. 2008 IEEE International Symposium on Circuits and Systems, Seattle, WA, USA, 2008: 240-243.
[16]	PARHI K K and OH D. Low-complexity switch network for reconfigurable LDPC decoders[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010, 18(1): 85-94. doi: 10.1109/TVLSI.2008.2007736.