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A Single Event Upset Fault Injection Method Based on Multi-clock for Aviation Environment |
Xue Qian-nan① Li Zhen② Jiang Cheng-xiang② Wang Peng① Tian Yi① |
①(Tianjin Key Laboratory for Civil Aircraft Airworthiness and Maintenance,Civil Aviation University of China, Tianjin 300300, China)
②(College of Safety Science & Engineering, Civil Aviation University of China, Tianjin 300300, China) |
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Abstract With the new electronic devices are increasingly used by airborne avionics equipment, Single Event Upset (SEU) fault has become a major hazard on aviation safety. Because of the randomness of SEU fault, the SEU fault occurs at any moments. Firstly, a multi-clock control is introduced to construct an SEU fault injection testing system. Secondly, the system simulates multi-time point of failure with real situations caused by single event upset effects. For sequential circuits constructed by SRAM-based FPGA, the influence of SEU is studied by the system and the failure data and failure rate of the undertest module is counted online. Two kinds of FPGA-based fault-tolerant circuit are tested by this system. Comparing with the traditional Triple Modular Redundancy (TMR) technology, the anti-SEU performance of the proposed multi-clock edge TMR reinforcement technology is improved about 1.86-fold. The experiment results verify that the proposed multi-clock SEU fault injection testing system is a quick, low-cost and highly accurate test for the single-event upsets fault, and demonstrate the effectiveness of the proposed SEU reinforcement technology.
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Received: 25 August 2013
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Corresponding Authors:
Xue Qian-nan
E-mail: qiannanxue@163.com
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[1] |
LIANG Huaguo, SUN Hongyun, SUN Jun, HUANG Zhengfeng, XU Xiumin, YI Maoxiang, OUYANG Yiming, LU Yingchun, YAN Aibin. FPGA-based Soft Error Sensitivity Analysis Method for Microprocessor[J]. JEIT, 2017, 39(1): 245-249. |
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