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| Parallel Voting RANSAC and Its Implementation on FPGA |
| Jiang Jie Ling Si-rui |
| Key Laboratory of Precision Opto-mechatronics Technology, Ministry of Education, Beihang University, Beijing 100191, China |
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Abstract RANdom SAmple Consensus (RANSAC) performs poor with the mass of data, high outliers ratio and complicated models. In this paper, a highly parallel voting version of RANSAC is presented. On the basis of parallelizing the hypothetical stage and generating multiple models simultaneously, a novel strategy of voting to determine whether a point belongs to inliers is proposed. Conventional search for the inliers relative to the best model is saved. On parallel platforms represented by FPGA, this algorithm can take advantage of the parallel architecture and characteristics to achieve deep-pipelined parallel computing. Experiments demonstrate the good robustness of the proposed algorithm and its considerable improvement of both speed and throughput.
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Received: 04 July 2013
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Corresponding Authors:
Ling Si-rui
E-mail: lingsirui@126.com
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| [1] |
LIANG Huaguo, SUN Hongyun, SUN Jun, HUANG Zhengfeng, XU Xiumin, YI Maoxiang, OUYANG Yiming, LU Yingchun, YAN Aibin. FPGA-based Soft Error Sensitivity Analysis Method for Microprocessor[J]. JEIT, 2017, 39(1): 245-249. |
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2014, Vol. 36 
