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| Pre-allocated Path Based Low Latency Router Architecture for Network-on-chip |
| Zheng Xiao-fu① Gu Hua-xi①② Yang Yin-tang③ Huang Zhong-fan① |
①(State Key Lab of ISN, Xidian University, Xi’an 710071, China)
②(Science and Technology on Information Transmission and Dissemination in Communication Networks Laboratory, Xidian University, Xi’an 710071, China)
③(School of Microelectronic, Xidian University, Xi’an 710071, China) |
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Abstract A low latency router architecture based Pre-Allocated Path Router (PAPR) is proposed for the Network-on-Chip (NoC). The advanced-routing algorithm and pre-allocated path are implemented to reduce the depth of the pipeline. The pre-allocated virtual channel arbitration is guaranteed by the advanced-routing. The packet transmission time in the network will not be affected even if the pre-allocation of virtual channel arbitration fails. The arbitration algorithm BSTS (Buffer Status ) takes the buffer status of the current node and downstream node into consideration. The new router not only reduces the packet waiting time in the buffer, but also lowers the probabilities of the idle buffer. According to the simulation results, compared with Generic Virtual Channel Router with iSLIP (GVCR-iSLIP) (iterative Round-Robin Matching with Serial Line Interface Protocal (SLIP)), the PAPR reduces the End To End (ETE) delay by 24.5% and improves the throughput by 27.5%; Compared with GVCR with Round-Robin Matching (RRM) (GVCR-RRM), the ETE delay is decreased by 39.2% and the throughput is increased by 47.2%. The router logic unit overhead and the power consumption are only increased by 8.9% and 5.9% respectively.
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Received: 29 May 2012
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Corresponding Authors:
Zheng Xiao-fu
E-mail: zhengxiaofu_1122@163.com
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2013, Vol. 35 
