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| AAC LC Decoder Design Optimization for Low-power Portable DAB Radio |
| Lu Ming-ying Zhang Li-li Wang Guo-yu Zhang Hong-sheng Li Liang-wei |
| Key Lab of Microelectronics Engineering, Chongqing University of Posts and Telecommunications, Chongqing 400065, China |
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Abstract In view of high power consumption of current Digital Audio Broadcasting (DAB) radio’s AAC+ decoder implemented in DSP processor, this paper proposes an ASIC design of low-power AAC LC decoder. The design achieves the most basic decoding DAB+ program with very low hardware cost, and realizes skillfully the compatibility of two different standards DAB+ and DAB after adding to the DAB decoder chip. In order to achieve low power consumption, this design optimizes the inverse quantization and IMDCT algorithm and uses the time-sharing method. The system clock runs at 16.384 MHz, adopts 0.18 μm CMOS technology, and power consumption is about 6.5 mW. Combined with the DAB channel decoder, it passes the real-time verification on the FPGA development board and completes the chip layout, and the chip area is 14 mm2.
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Received: 21 September 2010
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Corresponding Authors:
Zhang Li-li
E-mail: guodon-g-2007@163.com
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2011, Vol. 33 
