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| A New Low-Power High-Speed Prescaler in GNSS Receivers |
| Yu Yun-feng①; Ma Cheng-yan②; Ye Tian-chun① |
| ①Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; ②Hangzhou Zhongke Microelectronics Co., Ltd, Hangzhou 310053, China |
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Abstract A new prescaler based on new Source Coupled Logic(SCL) latch is proposed in this paper, supplying Local Oscillator (LO) for receivers. Compared to traditional static SCL latch, a clock-controlling transistor is added to reduce the time constant at sensing time, and as a result, the maximum operating frequency increases and the operating range is enlarged. A simple but to some extent accurate small signal model for this new architecture is developed, and the advantages of new design are described in detail. This prescaler’s maximum operating frequency can reach to 6.9 GHz when its current is only 1.2 mA. The prescaler is manufactured in 0.18 μm CMOS process, and it has been successfully applied to GPS receivers.
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Received: 03 June 2009
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Corresponding Authors:
Yu Yun-feng
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2010, Vol. 32 
