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| Design of Digital Down Converter of Mini SAR |
| Wang Hong-xian,Li Gang,Xing Meng-dao,Zhang Shou-hong |
| National Key Lab. of Radar Signal Processing, Xidian Univ., Xi’an 710071, China |
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Abstract In the designation of the real-time imaging machine of Mini SAR, the radar return signal is sampled in the intermediate frequency, then Digital Down Converter(DDC) is used to realize quadrature demodulate, which can reduce system complexity and improve radar’s performance. The difficulty in the design of the DDC of Mini SAR is firstly given in this paper, i.e. the sampling frequency is as high as 2Gsps and the bandwidth is 900MHz, which leads large difficulty in real-time processing. The optimal architecture of DDC based on real design parameters is given in the next, with the emphasis on the difference of the parallel FIR filter and fast FIR filter. Then the implementation of the DDC module using parallel processing with optimized structure in FPGA is given, the resource usage, running speed and quantity noise influence are given. Finally, the result of Mini SAR is given, which confirms the validity of the design.
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Received: 24 December 2008
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Corresponding Authors:
Wang Hong-xian
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LIANG Huaguo, SUN Hongyun, SUN Jun, HUANG Zhengfeng, XU Xiumin, YI Maoxiang, OUYANG Yiming, LU Yingchun, YAN Aibin. FPGA-based Soft Error Sensitivity Analysis Method for Microprocessor[J]. JEIT, 2017, 39(1): 245-249. |
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2010, Vol. 32 
