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| 0.8μm LDD CMOS RELIABILITY EXPERIMENTS AND ANALYSIS |
| Yu Shan①;Zhang Dingkang②; Huang Chang② |
| ①Institute of Computer Application and Simulation Technology, Second Academy, Ministry of Aero-Space Industry, Beijing 100854;②Shanxi Microelectronics Institute, Lintong 710600 |
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Abstract The numerical simulation of two dimensional device is conducted to describe the mechanism of the special substrate current and degradation of submi-cron LDD structure observed in experiments, and finally, the optimum processes for submicron LDD CMOS are proposed.
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Received: 20 April 1993
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1994, Vol. 16 
