时序电路的状态验证研究与设计

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Abstract It is very effective that use BDD to describe the synchronous circuits. This paper has proposed the reducing way for BDD in order to collapse the number of inputs, routes and states. Based on the features of circuit, several heuristic methods that speed up verification are presented.

Key words： Binary Decision Diagram（BDD） Node Collapsing Stata Transition Graph（STG）

Received: 06 March 1995

PACS:

TN799

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	He Xinhua
	Lu Changling
	Gong Yunzhan

Cite this article:

He Xinhua,Lu Changling,Gong Yunzhan. VERIFICATION DESIGNING FOR SYNCHRONOUS CIRCUITS[J]. , 1997, 19(4): 532-537 .

URL:

http://jeit.ie.ac.cn/EN/ OR http://jeit.ie.ac.cn/EN/Y1997/V19/I4/532

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