多层介质中通孔结构准静态电容参数的提取

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Abstract An efficient method to calculate the quasi-static capacitance of the via hole structure embedded in a multilayered dielectric media named Dimension Reduction Technique(DRT) is presented. Since the method takes full advantage of the characteristics of the stratified structure in integrated circuit, it can easily deal with the varied numbers of the dielectric layers as well as the varied structure parameters while only need little CPU time and memory space. The numerical results given in this paper are in good agreement with those of Ansoft’s software.

Key words： Parameter extraction Quasi-static capacitance 3D interconnect Via hole Dimension Reduction Technique（DRT）

Received: 24 April 1996

PACS:

TN431.2

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	Song Ben
	Hong Wei

Cite this article:

Song Ben,Hong Wei. CAPACITANCE EXTRACTION OF THE VIA HOLE STRUCTURE EMBEDDED IN THE MULTILAYERED DIELECTRIC MEDIA[J]. , 1998, 20(1): 109-113 .

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http://jeit.ie.ac.cn/EN/ OR http://jeit.ie.ac.cn/EN/Y1998/V20/I1/109