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| THE DESIGN AND IMPLEMENTATION OF AN FPGA-BASED DIGITAL HDTV VIDEO DECODER |
| Zhou Ping; Yu Sile |
| Institute of TV and Image Information Tianjin University Tianjin 300072 |
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Abstract This paper presents the scheme and its implementation of a video decoder, which can complete real-time decoding the MPEG-2 based coded bit stream. This scheme adopts the parallel processing technique, the operation in pipe line and a large quantity of FPGA. The approach for the motion compensation crossing the border, which is caused by parallel processing, is studied. The architecture of the decoder, the formation of main circuits and the realization of decoding procedue are described.
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Received: 02 September 1997
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1998, Vol. 20 
