时序电路的冗余状态变换确认研究

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Abstract The BDD (Binary Decision Diagram) is very important for representing synchronous circuits. After analyzing and reducing the BDD, the state traversing is proposed on the basis of collapsing of input, routes and states on STG. Finally, the verification for the non-reset circuits has been described.

Key words： Test generation Verification Finite-state-machines

Received: 14 May 1996

PACS:

TN79

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	He Xinhua
	Cai Hongliu
	Wang Weifeng

Cite this article:

He Xinhua,Cai Hongliu,Wang Weifeng. STATE TRANSITION REDUNDANCE IDENTIFICATION[J]. , 1999, 21(1): 141-144 .

URL:

http://jeit.ie.ac.cn/EN/ OR http://jeit.ie.ac.cn/EN/Y1999/V21/I1/141

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