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| A REAL-TIME 2-D DCT/IDCT PROCESSOR USING FPGAs |
| Xiang Hui; Teng Jianfu; Wang Chengning |
| Electronic Information Engineering College Tianjin University Tianjin 300072 |
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Abstract Based on the skew-circular convolution distributed algorithm presented by W.Li(1991). A 8×8 2-D DCT/IDCT processor has been designed using FPGAs, which can be used for HDTV s decoder or other signal and information processing systems. It can be used to calculate either DCT or IDCT depending on a single control line. AM of the input/output are 12-bit and the internal data bus and internal parameters are 16-bit.
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Received: 20 January 1998
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Jiang Zheng-hong, Lin Yu, Huang Zhi-hong, Yang Li-qun, Yang Hai-gang. Mapper for AIC-based FPGAs[J]. JEIT, 2015, 37(7): 1769-1773. |
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1999, Vol. 21 
