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| Reconfigurable Clustered Architecture of Block Cipher Processor |
| Meng Tao; Dai Zi-bin |
| Institute of Electronic Technology, Information Engineering University, Zhengzhou 450004, China |
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Abstract This paper presents the reconfigurable clustered architecture of block cipher processor. Appointed by instructions, the data-path of this architecture can be dynamically configured to be three modes, which includes 4clusters, 2clusters and single cluster mode. In different mode, different operations can be done, which improves the flexibility of this processor. Basing on clustered architecture, Explicit-decomposition low-power-design method is presented, which can reduce the power by 36.1%. With 5stages pipeline and wave-pipeline, this processor can work in a high rate. And the performances of AES/DES/IDEA reach 689.6Mbit/s, 400Mbit/s, 416.7Mbit/s.
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Received: 29 September 2007
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2009, Vol. 31 
