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| Optimized Decoder Design and Implement for High Rate LDPC Codes |
| Zhang Jing-lin; Liu Rong-ke;Zhao Ling |
| School of Elec. and Infor. Engineering, Beijing University of Aeronautics and Astronautics, Beijing 100083, China |
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Abstract This paper brings up with a hardware structure optimized method which is suitable for high code rate LDPC decoder, for example, CCSDS recommended LDPC (Low-Density Parity-Check code) code with ?code rate of 7/8. LDPC code with high code rate is usually concomitant with problem that row weight is far larger than the column weight. This optimized method is based on check matrix splitting, it also optimizes the common components of parallel decoder structure, and reduces complexity imbalance between Check Node processing Units (CNUs) and Variable Node processing Units (VNUs) existed in high code rate LDPC decoder. Thus, clock performance of the decoder is improved. Experiment has proved, compared with usual partial parallel decode structure, structure provided by this paper saves 41% hardware resources, and the code rate of partial parallel decode structure which adopts the same amount of hardware resources is just 75% than code rate of the structure in this paper.
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Received: 29 June 2007
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2009, Vol. 31 
