离散子波分解的专用芯片设计及CPLD实现

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Abstract The wavelet transform is a very effective mathematical tools for many fields such as signal processing and image coding, which is implemented by program in most cases. This paper presents a novel architecture suitable with CPLD chip for one- dimension DWT decomposition based on the relationship between wavelet transform and filter banks by rearranging the data in the processing of convolution and downsample by two. It possesses some practicable value with certain speed and decreased resources.

Key words： DWT Filter banks Downsample by two CPLD ASIC

Received: 21 July 1999

PACS:	TN495
	O177.6

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	Lno Feng
	Wu Shunjun
	Song Wanjie

Cite this article:

Lno Feng,Wu Shunjun,Song Wanjie. ASIC design and CPLD implementation for DWT decomposition[J]. , 2002, 24(2): 280-284 .

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http://jeit.ie.ac.cn/EN/ OR http://jeit.ie.ac.cn/EN/Y2002/V24/I2/280