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| Design and implementation of system control for the HDTV video decoder |
| Liu Jian; Li Hua; Wang Chengning; Yu Sile |
| School of Electronic Information Engineering Tianjin University Tianjin 300072 China |
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Abstract This paper presents the design and implementation of system control for HDTV video decoder. The principle of the system control is described in detail too. FPGA is adopted for its programmable and reconfigurable features. The system control works perfectly and steadily which ensures the perfect work of decoder and display buffer.
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Received: 28 April 2000
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LIANG Huaguo, SUN Hongyun, SUN Jun, HUANG Zhengfeng, XU Xiumin, YI Maoxiang, OUYANG Yiming, LU Yingchun, YAN Aibin. FPGA-based Soft Error Sensitivity Analysis Method for Microprocessor[J]. JEIT, 2017, 39(1): 245-249. |
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2002, Vol. 24 
