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| Hierarchical Modeling and Optimization of Versatile FPGA SB |
| Tan Jun; Shen Qiu-shi; Wang Ling-li; Tong Jia-rong |
| ASIC & System State Key Laboratory, Fudan University, Shanghai 201203, China |
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Abstract There are two restrictions in the Versatile Place and Route tool, VPR. It can only support three kinds of switch box architecture, which are Disjoint, Wilton and Universal, and the same type of wires in a channel must be distributed next to each other. To break through these two restrictions, this paper proposes a hierarchical versatile switch box model, covering arbitrary switch box architecture in FPGA. Based on this model, this paper designs new switch box architecture, JSB. Comparing with Disjoint, Wilton and Universal architecture, JSB improves greatly routability by 10.1%, 3.3% and 4.6% respectively. Furthermore, in this paper, optimizing the distribution of wires reduces the timing of critical path by 10.4% on average, compared with VPR.
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Received: 24 May 2007
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Corresponding Authors:
Wang Ling-li
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| [1] |
LIANG Huaguo, SUN Hongyun, SUN Jun, HUANG Zhengfeng, XU Xiumin, YI Maoxiang, OUYANG Yiming, LU Yingchun, YAN Aibin. FPGA-based Soft Error Sensitivity Analysis Method for Microprocessor[J]. JEIT, 2017, 39(1): 245-249. |
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2008, Vol. 30 
