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The FPGA implementation of the round robin scheduling algorithms |
Sun Huajin; Gao Deyuan; Zhang Shengbing |
Aviation Microelectronics Center Northwestern Poly technical University Xi an 710072 China |
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Abstract Round robin scheduling algorithm is a classic scheduling algorithm with many ap-plications. An FPGA implementation by using barrel shifter and pipelined priority encoder is presented in this paper with considering the FPGA structure characteristic and system’s requirement. And the performance and resource consumption of the implementation are dis-cussed. The test result shows that the implementation of the algorithm is effective and fit for the FPGA structure. The system with the implementation of algorithm runs very well.
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Received: 04 March 2002
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[1] |
LIANG Huaguo, SUN Hongyun, SUN Jun, HUANG Zhengfeng, XU Xiumin, YI Maoxiang, OUYANG Yiming, LU Yingchun, YAN Aibin. FPGA-based Soft Error Sensitivity Analysis Method for Microprocessor[J]. JEIT, 2017, 39(1): 245-249. |
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