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| An Improved Algorithm for Symbol Timing Recovery in a Multipath Fading Channel |
| Ai Bo①; Ge Jian-hua①; Zhao Yan-ni② |
| ①National Key Lab. of Integrated Service Networks.,Xidian Univ., Xi’an 710071 China;②Philips Datang Mobile TD-SCDMA UE R&D Cooperation Center Beijing 100083 China |
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Abstract This paper proposes a new improved algorithm for symbol timing recovery in a multipath fading channel through computer simulations. The computing equation is derived. Also, the correspondent FPGA hardware circuit is designed. Computer simulations and the testing process in the HDTV prototype prove its low complexity, easiness of realizing and excellent performance.
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Received: 23 September 2002
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Jiang Zheng-hong, Lin Yu, Huang Zhi-hong, Yang Li-qun, Yang Hai-gang. Mapper for AIC-based FPGAs[J]. JEIT, 2015, 37(7): 1769-1773. |
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2004, Vol. 26 
