|
|
|
| FPGA Watermarking Based on Modification of Time Constraints |
| Lu Jian-feng; Wang Shuo-zhong |
| School of Comm. and Info. Eng.,Shanghai Univ., Shanghai 200072 China |
|
|
|
|
Abstract Based on modification of time constraints in the FPGA design, a watermark-embedding scheme is proposed for protection of intellectual property rights of the system designer. A coded binary watermark sequence is used to replace the least significant digits of the time constraints in some non-critical paths. The modified time constraints lead to substantial and unique changes in the generated bit stream without altering the performance of the design, both in terms of space and time overheads and the system functionality. The embedded data can be extracted in a reverse procedure. The paper provides a scheme with zero area and low timing overheads, and a significant increase in embedding capacity in comparison with some existing techniques.
|
|
Received: 28 June 2003
|
|
|
|
|
|
| [1] |
Jiang Zheng-hong, Lin Yu, Huang Zhi-hong, Yang Li-qun, Yang Hai-gang. Mapper for AIC-based FPGAs[J]. JEIT, 2015, 37(7): 1769-1773. |
|
|
|
|
2004, Vol. 26 
